Search - vhdl image

[Graph program] jpeg_src

Description: 是jpeg标准下图象压缩的vhdl实现工程,包括core文件,测试文件,工程文件-image compression vhdl realization project under standard jpeg.core files, test files and project files are included.
Platform: | Size: 1569792 | Author: 石伟 | Hits:

[2D Graphic] XLIB

Description: 2D图像滤波VHDL代码。 2D图像滤波VHDL代码。-2D image filtering VHDL code. 2D image filtering VHDL code. 2D image filtering VHDL code.
Platform: | Size: 13312 | Author: leisuee | Hits:

[VHDL-FPGA-Verilog] shipingkonzhi

Description: 用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,
Platform: | Size: 431104 | Author: 张龙 | Hits:

[Other Embeded program] edge_detector

Description: 基于cpld的数字图像边缘检测算法的实现，vhdl源程序-CPLD-based digital image edge detection algorithm, vhdl source code
Platform: | Size: 1024 | Author: jjaai | Hits:

[Multimedia program] video_compression_systems.tar

Description: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Platform: | Size: 186368 | Author: 王弋妹 | Hits:

[Special Effects] the.implement.of.image.pretreatment.algorithm.in.t

Description: 现场可编程逻辑门阵列在实时数字图像处理中的应用-Field-programmable gate array logic in real-time digital image processing
Platform: | Size: 159744 | Author: 刘文娟 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: HDTV视频内容创作的繁荣以及在带宽受限的广播信道环境中传送这些视频内容的方法，不断催生新的视频压缩标准和相关视频图像处理设备。-HDTV video content creation and prosperity as well as bandwidth-constrained environment of the broadcasting channel to send video content of these methods, birth of a new video compression standards and associated video image processing equipment.
Platform: | Size: 59392 | Author: chenqunqin | Hits:

[VHDL-FPGA-Verilog] ImageProcessing

Description: 这个是国外大学的项目代码，这个是数字图像处理的模块-This is a project abroad, the University of code, this is a digital image processing module
Platform: | Size: 15399936 | Author: 陈晓 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG标准下图象压缩的VHDL实现工程，包含文档，原代码及测试代码-JPEG image compression standard of VHDL realization of the project, including documentation, source code and test code
Platform: | Size: 1474560 | Author: 王刚 | Hits:

[Special Effects] multilevel_filter

Description: 完整的多级滤波图像处理算法，利用FPGA实现，利用硬件结构实现算法能够满足苛刻的实时性要求。-Complete multi-level filtering image processing algorithms using FPGA realization algorithm using hardware structure able to meet the demanding requirements of real-time.
Platform: | Size: 588800 | Author: 朱磊 | Hits:

[VHDL-FPGA-Verilog] VHDL_CCD

Description: 用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!-VHDL language with the image sensor TCD132D realize the timing-driven code, timing accurate!
Platform: | Size: 69632 | Author: 曾娟丽 | Hits:

[VHDL-FPGA-Verilog] FPGAbi_ioreseach

Description: :针对现场可编程门阵列(FPGA)芯片的特点,研究FPGA中双向端口I/O的设计,同时给出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法,选用Xilinx的Spartan2E芯片设计一个多通道图像信号处理系统。-: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip to design a multi-channel image signal processing system.
Platform: | Size: 115712 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] JPEGvhdl

Description: JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
Platform: | Size: 260096 | Author: 姚大雷 | Hits:

[VHDL-FPGA-Verilog] 2DImageFilterByVHDL

Description: 用VHDL语言编程实现2维图像的滤波算法，简单精辟-VHDL programming language used to achieve 2-D image filtering algorithm, simple brilliant
Platform: | Size: 13312 | Author: 宋雪兵 | Hits:

[Graph program] vga

Description: 基于DE2板子的，VGA 图像显示，采用verilog语言-Based on the DE2 board, VGA image display, using Verilog language
Platform: | Size: 1024 | Author: 张梦 | Hits:

[VHDL-FPGA-Verilog] husw

Description: 用VHDL语言设计维特比解码器是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Platform: | Size: 1024 | Author: hsw0320 | Hits:

[Other] 23

Description: 图像技术的应用：包括：基于FPGA的图像处理系统；基于图像特征的景象匹配辅助导航系统中的关键技术研究；图像导航技术的发展和应用 -Application of imaging technology: including: FPGA-based image processing system images based on image feature matching assisted navigation system in the research of key technologies image navigation technology development and application of
Platform: | Size: 4107264 | Author: 李灵 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Software Engineering] Digital_Filter_implementation_by_FPGA

Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Platform: | Size: 1969152 | Author: carol | Hits:

[VHDL-FPGA-Verilog] Vhdl-Image-Processing

Description: Vhdl-Image-Processing
Platform: | Size: 4657152 | Author: commando | Hits:

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